The present invention relates to a method for fabricating a nonvolatile semiconductor memory device including a tunnel insulating film, and more particularly relates to a nonvolatile semiconductor memory device that can eliminate crystal defects from parts of a source or drain region under an end of a floating gate electrode.
A known nonvolatile semiconductor memory device and a method of fabricating the device will be described, with reference to the drawings.
FIGS. 2A through 2C are a typical method for fabricating a known stacked nonvolatile semiconductor memory device and illustrate cross-sectional structures corresponding to respective process steps.
First, as shown in FIG. 2A, a tunnel oxide film 103 is formed by thermal oxidation on a transistor region defined in a p-type silicon substrate 101 by an isolation film 102. Then, a staked cell electrode 107, consisting of floating gate electrode 104, capacitive insulating film 105, and control gate electrode 106, is formed on the tunnel oxide film 103. Thereafter, a silicon dioxide film 108 having a thickness of about 30 nm, for example, is deposited by a chemical vapor deposition (CVD) process over the substrate 101 as well as over the stacked cell electrode 107.
Next, as shown in FIG. 2B, arsenic ions are selectively implanted into the substrate 101 to form a source region 109 so that an edge of the source region 109 reaches a region under one end of the tunnel oxide film 103. Then, ions of boron, which is a p-type dopant of the same conductivity type as the dopant already introduced into the substrate 101, are selectively implanted into a part of the substrate 101 under the floating gate electrode 104 and in the vicinity of the edge of the source region 109 by a large-angle-tilt ion implantation technique. As a result, a threshold voltage setting region 110 for determining the threshold voltage of a memory cell is formed. Thereafter, the source region 109 is masked and arsenic ions are implanted into the substrate 101 to form a drain region 111 so that an edge of the drain region 111 reaches a region under the other end of the tunnel oxide film 103.
Then, as shown in FIG. 2C, the substrate 101 is annealed in an oxidizing ambient to activate the dopants implanted into the source/drain regions 109 and 111. The annealing process is performed in the oxidizing ambient to increase the thickness of the tunnel oxide film 103 at both ends thereof along the gate length of the floating gate electrode 104.
In this process, arsenic ions, which easily do damage on the silicon dioxide film 108, are implanted into the source region 109. In addition, the edge of the source region 109 reaches the region under the end of the tunnel oxide film 103. Furthermore, the large-angle-tilt ion implantation is performed to form the threshold voltage setting region 110. As a result, both ends of the tunnel oxide film 103 in the gate length direction are damaged by the implantation and have its quality degraded. In order to repair the damage, the tunnel oxide film 103 is thickened at both ends in the gate length direction.
A stacked nonvolatile semiconductor memory device stores data thereon by storing charge in the floating gate electrode 104. Thus, the device needs to exhibit a charge retention characteristic, i.e., charge should not leak into the substrate 101 so easily. The charge retention characteristic degrades partly because crystal defects are likely created in part of the source or drain region 109 or 111 under the tunnel oxide film 103.
When crystal defects are created in that part under the tunnel oxide film 103, the tunnel oxide film 103 is strained or a charge trap level is produced. As a result, charge is much more likely to leak into the substrate 101.
In the known method for fabricating the nonvolatile semiconductor memory device, ions are implanted for the source/drain regions 109 and 111 via the relatively thin silicon dioxide film 108 to protect the ends of the tunnel oxide film 103. Further, the silicon dioxide film 108 is coated with a masking resist for the ion implantation processes and cleaned to remove the masking resist. Thus, the thickness of the silicon dioxide film 108 changes because of implant-induced damage, contamination, and cleaning. If the dopants existing in the ion implanted regions are activated in such a state by annealing the substrate in an oxidizing ambient, oxidation-induced defects or doping-induced defects are likely created.
In a stacked nonvolatile semiconductor memory device, a source region 109 with a shallow junction and a low resistivity should be formed by implanting arsenic ions to reduce the width of a gate electrode while securing a sufficient operating current for a memory cell. For that purpose, the source region 109 is formed to have one edge reaching the region under the end of the tunnel oxide film 103 in the gate length direction. In addition, boron ions for controlling the threshold voltage of the memory cell are also implanted into the region under the tunnel oxide film 103 by the large-angle-tilt ion implantation. As a result, as shown in FIG. 2C, a crystal defect D1 is created under the tunnel oxide film 103, when the dopant existing in the source region 109 is activated.
Furthermore, to reduce the resistivity of the drain region 111, arsenic ions are implanted so that one edge of the drain region 111 reaches a region under the tunnel oxide film 103. As a result, a crystal defect D2 might be created in the drain region as in the source region 109.
It is therefore an object of the present invention to eliminate crystal defects from a part of a substrate under a tunnel oxide film in a nonvolatile semiconductor memory device.
In order to achieve this object, according to the present invention, a passivation film, which has been used for protecting a tunnel insulating film in ion implantation processes, is renewed, i.e., replaced with a new one before dopants introduced into the ion implanted regions are activated. And then the dopants introduced are activated in an inert gas ambient.
Specifically, an inventive method for fabricating a non-volatile semiconductor memory device includes the steps of: a) forming a tunnel insulating film on a substrate and then selectively forming a floating gate electrode on the tunnel insulating film; b) forming a first passivation film on first and second regions of the substrate, the first and second regions being located below the floating gate electrode to horizontally sandwich the floating gate electrode therebetween; c) implanting ions of a first dopant into the substrate through the first passivation film with second region masked, thereby defining a doped region in the first region so that the doped region reaches a third region of the substrate, the third region being located around an end of the first region; d) removing the first passivation film and then forming a second passivation film on the first and second regions; and e) annealing the substrate, on which the second passivation film has been formed, in an inert gas ambient, thereby activating the first dopant in the doped region.
According to the inventive method, the first passivation film, which has been damaged during the ion implantation process, is replaced with the second passivation film having a good quality and covering the doped region. Then, the dopant in the doped region is activated by annealing in an inert gas ambient. Thus, neither oxidation-induced defects nor dopant-induced defects are created in a part of the doped region under an end of the floating gate electrode. As a result, a stress placed on the tunnel insulating film can be reduced and the charge retention characteristic of the device improves.
In one embodiment of the present invention, the step d) may comprise forming the second passivation film by performing a chemical vapor deposition process at such a temperature as not activating the dopant in the doped region. In such an embodiment, it is possible to prevent the dopant in the doped region from being activated before the second passivation film is formed.
In another embodiment, the method may further include the step f) of annealing the substrate in an oxidizing gas ambient, thereby thickening the tunnel insulating film at both ends thereof along the length of the floating gate electrode. The step f) may be performed after the step e) has been performed. In such an embodiment, it is possible to lessen the damage to be done on the tunnel insulating film by ion implantation at both ends thereof along the length of the floating gate electrode.
In still another embodiment, the doped region may be a source region, and the method may further include the step g) of implanting ions of a second dopant into the substrate through the first passivation film with the second region masked, thereby defining a threshold voltage setting region in the third region of the substrate. The step g) may be performed between the steps c) and d). In such an embodiment, the semiconductor memory device can operate as intended.
In yet another embodiment, the doped region may be a first drain region having a shallow junction, and the method may further include the step h) of implanting ions of a second dopant into the substrate through the first passivation film with the second region masked, thereby defining a second drain region that expands under the first drain region. The first and second dopants may be of the same conductivity type. The step h) may be performed between the steps c) and d). In such an embodiment, the second drain region is defined under the first drain region, and the drain region can have its junction breakdown strength increased.